RISC-V Foundational Associate (RVFA) Study Guide


How to Prepare for the RISC-V Exam?

Preparing for the RISC-V Foundational Associate Exam (RVFA) certification exam? Don’t know where to start? This post is the RISC-V Foundational Associate (RVFA) Certificate Study Guide (with links to each exam objective).

I have curated a list of articles from the Internet for each objective of the RVFA exam. I hope this article will help you to achieve the RISC-V Foundational Associate (RVFA) Certification. Also, please share the post within your circles so it helps them to prepare for the exam.

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RISC-V Foundational Associate (RVFA) Course

Linux FoundationRISC-V Fundamentals
UdemyEmbedded Fun with RISC-V
Amazon e-book (PDF)Design Computer Architecture, RISC-V Edition

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Using RVFA exam dumps can get you permanently banned from taking any future certificate exams. However, I strongly suggest you validate your understanding with practice questions.

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RISC-V Overview 10%

History of RISC-V: The Free and Open ISA

History – RISC-V International

What is RISC-V?

RISC-V International

RISC-V International – RISC-V: The Open Standard RISC Instruction Set Architecture

RISC-V Documentation

RISC-V Instruction Set Manual

Contribute to RISC-V

RISC-V Learn Contribute

Where to start with RISC-V?

RISC-V Instruction Set Architecture 35%

RV32I and RV64I

RV32I, RV64I Instructions


Understand Instruction Formats: branching, accessing memory, and accessing data structures

RISC-V Branch Instructions

RISC-V Instruction-Set Cheatsheet

Understand the modularity of RISC-V as an ISA: core ratified (M, C, F, D, A) and other extensions

Towards a Modular RISC-V Based Many-Core Architecture for FPGA Accelerators

Understand Privilege Modes, system calls, CSRs, exceptions, and interrupt handling

RISC-V Privilege Levels and System Startup

System Calls: RISCV OS in Rust

Control and Status Registers

Exceptions and Interrupts

Understand memory model, cache management, and virtual memory management

Memory Consistency model

Cache Management Operations for RISC-V

Assembly Language for RISC-V 25%

Understand RISC-V specific assembly language syntax and features, including CSR access

RISC-V Assembly Language

RISC-V CSR access

Write and debug RISC-V assembly code

RISC-V Assembly for Beginners

RISC-V External Debug Support

Assess the performance of assembly code

Assembly Programming with RISC-V – Part 1

Assembly Programming with RISC-V: Part 2

Convert high-level code to assembly code

Translating High-level language into Assembly language

High-Level Languages for RISC-V: C Programming 15%

Understand RISC-V tools including compilers, debuggers, simulators, performance tools, OSes, and SDKs

GNU toolchain for RISC-V, including GCC

Working with High-Level-Language Debuggers in RISC-V-Based apps

Spike, a RISC-V ISA Simulator

Understand calling conventions (ABIs), the stack, and disassembly

RISCV calling convention

Online RISC-V disassembler

Understand inline assembly

RISC-V inline assembly

How to use Inline Assembly Language in C Code

RISC-V Operating Systems & Tools 15%

Fundamentals of Operating Systems including implementing basic OS functionality in RISC-V ASM

RISC-V assembly for beginners

Understanding the basic use and functionality of firmware for RISC-V platforms

RISC-V – Firmware Security

Understanding microcontrollers versus application processors

Microcontroller vs Microprocessor

Running RISC-V Applications in a General Purpose OS

What is Needed to Support an Operating System?

This brings us to the end of the RISC-V Foundational Associate (RVFA) study guide.

What do you think? Let me know in the comments section if I have missed out on anything. Also, I love to hear from you about how your preparation is going on!

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